The present invention relates to the electrical, electronic, and computer arts, and, more particularly, to methods for cutting fins in integrated circuits comprising FinFETs.
Multi-gate field-effect transistors (FETs) are of considerable interest because of their superior electrostatic integrity, as well as their promise of lower supply voltages, reduced threshold voltages, and extended scalability. FinFETs are one form of such multi-gate device. In a FinFET, a narrow channel feature (i.e., fin) is raised above the substrate and passes under a gate, which effectively wraps around the fin. The gate is thereby capacitively coupled to the top as well as the sides of the fin. So structured, very little leakage current passes through channel portions of the fin when the device is in the off state. This allows the use of lower threshold voltages and higher switching speeds.
A single fin may initially be patterned to span across regions that will ultimately be separated into multiple FinFETs. Later, after forming additional elements such as gates and contacts, the fin may be cut to isolate one transistor from another. Ideally, such cutting will utilize as small an area as possible. Nevertheless, cutting just the fins without simultaneously damaging the nearby structures remains challenging. Gas phase plasmas, for example, may be made somewhat selective to silicon, but have enough plasma potential to also etch nearby dielectric materials.